Replacing the polysilicon gate with a metal gate will essentially. Our 28nm platform is based on industry mainstream technology that includes conventional polyoxynitride process and gate last, high k metal gate, which provides superior performance over gate first high k offerings. High k metal gate stacks have been extensively investigated in the context of cmos logic, both for gate. Highkmetal gate the technology in an intel chip that enabled the fabrication of 45 nm microprocessors in 2007. He obtained his academic degrees from the institute of solid state physics of the chinese academy of sciences. High k materials such as al 2 o 3 and hfo 2 are widely used as gate dielectrics in graphene devices. High performance 2220nm finfet cmos devices with advanced. Two different integration approaches have been implemented in high volume production. Chau and colleagues explained the problem that led to the use of a metal gate in detail in high k metal gate stack and its mosfet characteristics, ieee electron. Highkmetal gate technology represents a fundamental and their effect reduce with geometrical scaling ofthe chip. However, different schemes to integrate those novel materials have been recently proposed, traditionally referred to as gate first and gate.
For high k metal gate integration, one of the major challenges with gate first flow is to achieve and maintain desired effective work function and eot after high thermal budget. The availability of highkmetal gate technology offers quite a few advantages in terms of power reduction. The use of high k will allow a significant reduction of the equivalent oxide thickness of the gate dielectric itself. The second feature is the extension of 193nm dry lithography to the 45nm technology node pitches. Requirements of high k oxides among the various requirements of gate dielectric materials, the most important are good insulating properties and capacitance performance fig. Integration of highkmetal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory dram technology. However, the effective work function values of metal gate. In addition to the pmos nbti, nmos pbti degradation has been observed 1. Gate first flow requires high thermal uniformity with different rfpvd tn process budget after metal gate process, which limits work conditions on si02 gatc. Enabling effective work function tuning by rfpvd nmos. It is necessary to replace the sio2 with a physically thicker layer of oxides of higher dielectric constant. The first metal deposit on the gate area is the pmos work function metal, followed by the nmos work function metal the pmos metal is removed from nmos transistors prior to deposition of the second work function metal.
Dielectric breakdown in a 45 nm highkmetal gate process. Like other technology components of the semiconductor industry, the highkmetal gate has also continued innovation since its introduction to the 45 nm node. Highk materials and metal gates for cmos applications. Mismatch in high k metal gate process analog design, ieee international electron devices meeting, 18. Aug 24, 2012 he obtained his academic degrees from the institute of solid state physics of the chinese academy of sciences. The gate dielectric consists of a highk material the gate electrode is made of metal intel has succeeded in integrating these innovations and creating transistors with recordsetting performance, and with dramatically reduced current leakage intel believes that high kmetal gate can be implemented in the 45nm manufacturing. As elements in the chip were being reduced to 45 nanometers, the gate dielectric began to lose its insulating dielectric quality and exhibited too much leakage. Complete dfm model for high performance computing socs. Ma yale university, center for microelectronics, and department of electrical engineering new haven, ct 065208284 introduction high k dielectrics are being actively pursued by the semiconductor industry to replace sio2 as the gate dielectric for future generations of cmos transistors. Silicon dioxide sio 2 has been used as a gate oxide material for decades. Metal gate high k dielectric stack metal gate elect rodes may be more effective than polysi in screening the high k so phonons from coupling to the channel under inversion conditions, resulting in improved channel mobility 78. Advanced metal gatehighk dielectric stacks for high. Intel made a significant breakthrough in the 45nm process by using a highk hi k material called hafnium to replace the transistors silicon dioxide gate dielectric. This new technology incorporates a high k dielectric, which reduces leakage and improves the dielectric constant.
A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are a. New materials for the gate stack of mostransistors. The scaling of feature size, gate length, and oxide thickness according to. Device scaling ofhigh performance mosfet with metal gate. Globalfoundries, intel, tsmc and umc are developing andor expanding their efforts at. However, the use of high k metal gate require a ntype metal and a ptype. Pdf highkmetal gates in leading edge silicon devices. The socalled gatefirst metal inserted polysi and gatelast replacement metal gate approaches have both pros and cons, as summarized in fig. Jae king liu department of electrical engineering and computer sciences university of california, berkeley, ca 94720. Intel made a significant breakthrough in the 45nm process by using a high k hi k material called hafnium to replace the transistors silicon dioxide gate dielectric, and by using new metals to replace the n and pmos polysilicon gate electrodes. May 11, 2017 once youve replace the sio2 gate oxide with highk dielectrics hafnium oxide or zirconium oxide you band diagram is completely different. The incorporation of high k dielectrics with metal gates into a manufacturable, high volume transistor process is the result of tremendous ingenuity and effort by many scientists and engineers 1. Comprehensive and systematic design of metalhighk gate.
High k \ metal gate stack shows significantly lower gate leakage than sio2. One way to achieve the desired effective work function is to use dipole effect by adding metal elements into high k dielectric film 12. They showed a working sram array with good process yield, performance, and reliability. Metal gates and work function materials are required to adjust fermi levels and are essential for device performance. Compared to the gate first technology, the gate last offering provides more advantages, including lower leakage current and better chip performance.
High k gate dielectrics for future cmos technology t. Enabling metal depostition technology for highk metal. As a result, a dipole is formed between high k and metal gate, leading to a work function lowering. The remaining gate space is filled with aluminum and excess is polished away to leave a finished high k metal gate transistor. The sio2 eot of the hk plus the interface layer il that forms between the hk and the silicon is 1. We show that the performance of hkmg transistors has a strong dependency on the.
His research interests and efforts cover the areas of the preparation, characterization, fundamental understanding and associated applications of high k gate dielectric thin. Dual workfunction wf with an advanced high k metal gate hkmg stack is deployed in an integrationfriendly cmos process flow. High k metal gate hkmg technology has become one of the frontrunners for the next generation of cmos devices. Pdf highkmetal gate stacks in gate first and replacement. Lowpower dramcompatible replacement gate highkmetal gate. Recent trend from topdown lithography to selfalignment and bottomup patterning approaches source. High metal gate technology is on the verge of replacing conventional oxynitride dielectrics in stateoftheart transistors for both high performance and lowpower applications. The silicon gates replaced aluminum gatesthe metal in metaloxide semiconductor in work described in the 1969 ieee spectrum article. High kmetal gate the technology in an intel chip that enabled the fabrication of 45 nm microprocessors in 2007. The past, present and future of highkmetal gates citeseerx. However, different schemes to integrate those novel materials have been recently proposed, traditionally referred to as gate first and gate last. High k hk dielectrics are a solution to overcome these limitations.
Gang he is professor at the school of physics and materials science of the anhui university, china. Work function setting in highk metal gate devices intechopen. There is certainly a benefit to moving from 40nm to 28nm. His research interests and efforts cover the areas of the preparation, characterization, fundamental understanding and associated applications of high k gate dielectric thin films. High k \metal gate stack achieves nmos and pmos channel mobility close to sio2s. When the gate is pulsed, current flows between the source and drain. The evolution of highk metal gate transistors, from the first planar 45nm to the latest 14nm node. The scaling of complementary metal oxide semiconductor cmos transistors has led to the silicon dioxide layer used as a gate dielectric becoming so. The incorporation of high k dielectrics with metal gates into a manufacturable, high volume transistor process is the result of tremendous ingenuity and effort by many scientists and engineers. Like other technology components of the semiconductor industry, the highk metal gate has also continued innovation since its introduction to the 45 nm node. However, there are additional factors such as polysilicondepletion effect pde contributing to the total cet of gate dielectrics1.
Pdf 2007 saw the introduction of the first highkmetal gate hkmg devices into the marketplace. Direct tunneling leakage current start to flow when the thickness is 3 nm. Osburn north carolina state university, raleigh, nc 27695 introduction high k gate dielectrics and metal gates are being widely studied for next generation devices,s dry etched and all the other zro. Then, workfunction metal electrodes are deposited followed by a gate fill process. Thanks to the higher permittivity of hfalon, peak transconductance was. As transistor size continues to shrink, sio2polysilicon gate stack has been replaced by highkmetal gate to enable further scaling. High dielectric constant oxides stanford university. High performance 32nm logic technology featuring 2nd. Dualepitaxy and multiple stressors are essential to boost the device performance. Tsmcs industryleading 28nm process technology mainly uses high k metal gate hkmg gate last technology. High k \ metal gate stack achieves nmos and pmos channel mobility close to sio2s. High k \metal gate stack shows significantly lower gate leakage than sio2. Why is a metal used instead of polysilicon for highk gate. However, integration in dram periphery poses unique constraints on the choice of materials and process.
Ald highk as a common gate stack solution for nano. As transistor size continues to shrink, sio2polysilicon gate stack has been replaced by high k metal gate to enable further scaling. Ald highk as a common gate stack solution for nanoelectronics. High k metal gate stacks in gate first and replacement gate schemes. However, the effective work function values of metal gate in graphene fet are significantly. Intel made a significant breakthrough in the 45nm process by using a highk hik material called hafnium to replace the transistors silicon dioxide gate dielectric. As metaloxidesemiconductor fieldeffect transistors mosfets have decreased in size, the thickness of the silicon dioxide gate dielectric has steadily decreased to increase the gate capacitance and thereby drive current, raising device performance. The gate dielectric consists of a high k material the gate electrode is made of metal intel has succeeded in integrating these innovations and creating transistors with recordsetting performance, and with dramatically reduced current leakage intel believes that highkmetal gate can be implemented in the 45nm manufacturing. Chau and colleagues explained the problem that led to the use of a metal gate in detail in highkmetalgate stack and its mosfet characteristics, ieee electron. Device scaling ofhigh performance mosfet with metal gate high k at 32nm technologynode andbeyond xinlin wang, ghavam shahidi, phil oldiges and mukesh khare ibm semiconductor research and development center systems and technology group, hopewell junction, ny 12533, research division, ibm t.
The evolution of high k metal gate transistors, from the first planar 45nm to the latest 14nm node. In both integration schemes, getting the right work functions and threshold voltages for ntype. Cmos integration of highkmetal gate transistors in. Work functions for nmos and pmos breakthroughs with metal gates ntype metal and ptype metal with the correct work functions on high k have been engineered. Kirsch, prashant majhi, byoung hun lee atomic layer deposition of high k dielectric and metal gate stacks for mos devices atomic layer deposition of highhigh k dielectric and metal gate k dielectric and metal gate stacks for mos devices. Cmp solutions for the integration of high k metal gate. Hfsio has a lower k value than hafnium oxide, but could provide higher crystallization temperature and higher mobility. Intels high k metal gate technology enabled elements on a chip to be reduced to 45 nm with stability. Challenges in spacer process development for leading. This paper mainly focuses on diffusion od dummy fill because the diffusion uniformity is directly related with shallow trench isolation sti and. Over years was the material of choice as gate insulator. Unacceptably high levels of bti degradation in both nmos and pmos are observed on hk with preexisting defects and of poor. This marked the return of metal gate technology on silicon for the first time since polysilicon gates.